Low-k dielectric material plus copper (Cu) dual damascene interconnect structures are well known to those skilled in the semiconductor art to be the choice for high speed and reliable signal transmission in VLSI, particularly as device feature sizes on an IC continue to scale down. While having extremely low-k value to significantly reduce inter/intra-metal layer capacitance, which in turn reduces signal RC delays and enhance signal integrity, porous low-k (PLK) dielectric materials have been facing some major technical obstacles to be fully integrated into existing IC manufacturing processes. Among those obstacles are poor control on k value and material hardness, poor control on etch rate, poor control on the etch profile in the time-controlling controlling trench etching process, poor trench/via bottom roughness, poor mechanical strength to survive chemical-mechanical polishing (CMP), and so on. These drawbacks and others in the prior art lead to poor device performance and poor device reliability, such as large variations in the metal conductor resistance due to large variations in trench depth, higher inter-metal layer capacitance due to rough trench bottoms, harmful copper diffusion due to rough via bottoms, poor device reliability due to poor interface adhesion on the rough via bottoms and/or discontinuous Cu/TaN/PLK interfaces on the rough trench bottoms, severe CMP recesses in trench dielectric due to poor material hardness and the like.
Costly extra processes have been employed to ease those problems. For instance, a separate CMP polish stop layer is deposited atop the dual damascene stack to protect the top dielectric layer from aggressive polishing and cleaning, and further acts as a CMP stop. A dedicated trench etch stop layer is fabricated between via and trench dielectrics in order to have a good control on trench etch profile. These extra processing steps, which only partially solve the above described problems, demand extra processing resources, and thus raise the overall fabricating costs.
In view of these and other problems in the prior efforts to integrate low-k dielectric into existing fabricating processes, there is a need for improved or new low-k dielectric interconnect structures and methods of fabricating the same.